Bosch RTC (Research and Technology Center), Palo Alto, CA

Project

Performed measurements and data post-processing on a 16-bit scalable incremental ADC using MATLAB and Simulink.

• ADC digital interface was implemented on a multi-rate Xilinx FPGA.
• Decimation filter ran at ADC sample rate while USB interface and ADC controls ran at a higher rate.
• Interfering tones on measurement setup were eliminated.
• Peak SFDR of 98 dB and peak SNDR of 81.5 dB were achieved.
• ADC board schematic design and part of layout were modified.